The PhD project aims to develop, design, and implement memristor-based in-memory computing edge AI engines. It will use analog computing for the key kernels of neural networks (multiply and accumulate operations) in which the memristors mimicking the synapse are structured in a compact crossbar architecture. To optimise the energy and enhance the reliability, different schemes will be explored, including different cell structures of the crossbar (e.g., 1T1R, 2T2R, 2T1R) while using crossbar-periphery codesign; current-based reading versus voltage-based reading of the crossbar, reliability aware mapping of the weights in the crossbar such as bits slicing, detection and recovery from read disturb which is a major concern for RRAM memristors, etc.

Recruitment host: Delft University of Technology, Delft, Netherlands

Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla

Cross-sectoral co-supervision: Dr. Saad Saleh, IMEC-NL, Netherlands

Contact: Prof. Said Hamdioui, s.hamdioui@tudelft.nl

More details at the host webpage:

• This PhD position at TU Delft

The PhD project aims to explore and develop fault models using EDA tools, explore safety analysis methodologies using functional testing techniques, or use metric-driven verification methodologies for AI accelerators. The project will also exploit and optimise safety verification techniques such as simulation-based fault injection or formal verification techniques. The solutions will be integrated into the overall EDA tool flow to provide an advanced methodology flow incorporating EDA practices to optimise safety and accelerate time-to-market for AI accelerator designs.

Recruitment host: Cadence Design Systems, Munich, Germany

Supervisors: Dr. Hans-Martin Bluethgen, Dr. Felipe Augusto da Silva

Cross-sectoral co-supervision (PhD studies): Prof. Said Hamdioui, Delft University of Technology, Netherlands

Contact: Dr. Ahmet Cagri Bagbaba, abagbaba@cadence.com

More details at the host webpage:

• This vacancy at Cadence Careers

The performance of AI accelerators often highly influenced by the memory interface. With new packaging approaches like Chiplets or 3D integration, a new concept for high-bandwidth memory integration between the memory and the AI accelerator can be explored. This PhD project aims to develop a disruptive concept of memory integration based on advanced packaging options. It will consider the development of a highly innovative design methodology for fast and easy design of different memory integration options based on different package types.

Recruitment host: Fraunhofer-Gesellschaft, Dresden, Germany

Supervisors: Dr. Benjamin Prautsch, Andy Heinig

Cross-sectoral co-supervision: Dr. Felipe Augusto da Silva, Cadence Design Systems, Germany

Co-supervision (PhD studies): Prof. Said Hamdioui, Delft University of Technology, Netherlands

Contact: Andy Heinig, andy.heinig@eas.iis.fraunhofer.de

(more details at the host webpage - TBD)

In this PhD project, the researcher will develop non-ideality/reliability aware mapping and quantisation schemes to tolerate the impact of memristive devices non-ideality on the computational accuracy without compromising on energy efficiency. Non-idealities-aware training schemes will also be investigated. They will also explore dynamic neural network models to dynamically deal with memristive non-idealities; different schemes, such as mapping defective cell/row to a redundant cell/row, defective cell/block disabling schemes, will be explored and their impact on the model’s accuracy and energy-efficiency will be studied.

Recruitment host: Delft University of Technology, Delft, Netherlands

Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla

Cross-sectoral co-supervision: Dr. Manolis Sifalakis, IMEC-NL, Netherlands

Contact: Prof. Said Hamdioui, s.hamdioui@tudelft.nl

More details at the host webpage:

• This PhD position at TU Delft