DC1.1-TUT "Reliable RISC-V based Architectures for Edge AI"

Ashwin Santhosh

Recruiting institution: Dept. of Computer Systems, Tallinn University of Technology, Estonia
Supervisors: Prof. Maksim Jenihhin, Dr. Artur Jutman
Cross-sectoral co-supervisor: Dr. Wolfgang Ecker, Dr. Endri Kaja, Infineon Technologies, Germany
Recruitment period: 07.02.2025 – 06.02.2028 (36 months)
PhD studies: Tallinn University of Technology

DC background

Ashwin Santhosh earned a bachelor’s degree in Electronics and Communication Engineering from Bangalore Technological Institute, India, before joining Samsung R&D as part of the Bixby Voice Intelligence team, where he advanced to Associate Engineer, led a team of 10 data annotators, and received the Best Employee Award. He later completed a Master of Technology in Very Large-Scale Integration at Amrita University, publishing research on efficient Ternary Content Addressable Memory (TCAM) design implemented on Field-Programmable Gate Arrays (FPGA). To expand his international exposure, Ashwin pursued a Master of Science in Information and Electrical Engineering at Hochschule Wismar, Germany, while working as a Research Assistant at Forschungszentrum Informatik (FZI) and Fraunhofer IMS, contributing to FPGA prototyping and processor–FPGA integration. For his Master’s thesis with Robert Bosch Research, he developed fault-tolerant interconnect architectures for neural network computation in automotive Electronic Control Units (ECUs), focusing on ISO 26262 safety standards, reliability, and fail-operational design requirements, and earned the highest grade. These experiences form the foundation of his PhD research on reliable RISC-V–based architectures for edge AI.

Individual research project 

This individual research project focuses on developing low-cost, ultra–low-power open-source RISC-V accelerators for edge AI, with reliability and safety as primary objectives. Since hardware cannot be modified after fabrication, fault tolerance is embedded from the design stage, combining architectural optimisation with robust monitoring and recovery mechanisms. The work introduces a layered approach: local processor- and accelerator-level protections using both vendor-supported and custom techniques, complemented by a system-level health processor that gathers data from distributed sensors and IJTAG-based instruments. This unit enables coordinated fault handling and predictive maintenance to ensure dependable operation over time. Expected outcomes include an open-source RISC-V edge AI prototype with hierarchical fault management, in-field fault detection and recovery infrastructure, and demonstrations of how energy-efficient open hardware can be extended with advanced reliability features for long-term resilience.

DC1.2-IMEC "Digital in-memory brain inspired edge processors for Edge AI"

Lorenzo Zucchini

Recruiting institution: IMEC-NL, Eindhoven, Netherlands
Supervisor(s): , Dr. Saad Saleh
Cross-sectoral co-supervisor: Prof. Said Hamdioui, Dr. Mottaqiallah Taouil, Delft University of Technology, Netherlands
Recruitment period: 16.03.2025 – 15.03.2028 (36 months)
PhD studies: Delft University of Technology

DC background

Lorenzo Zucchini holds a BSc in Electronic Engineering (2020) and an MSc in Electronic Engineering, Smart Connected Systems (2023), both from the University of Modena and Reggio Emilia (Modena, MO, Italy). During his Master's studies, he specialized in micro- and nanoelectronic devices, as well as in emerging non-volatile memory technologies. His Master's thesis focused on the effects of hardware-aware training in addressing parasitic resistances within Resistive RAM (RRAM)-based crossbar arrays.

Individual research project 

Brief overview of research project and major accomplishments expected

This MSCA project aims to develop a novel brain-inspired architecture that leverages in-memory computing to overcome the von Neumann bottleneck—the performance limitation caused by the separation between memory and logic units. While in-memory computing has attracted considerable attention in the research community, most existing work has focused on analog implementations, which are inherently susceptible to noise and device variability. Moreover, these analog approaches often rely on emerging non-volatile memory technologies that are still in their early stages of development and require further investigation.

To address these limitations, this project will focus on digital in-memory computing architectures based on Static RAM (SRAM), a mature and well-established technology. Specifically, the project aims to design and develop a new digital in-memory computing architecture that significantly enhances computational throughput and lowers latency in AI-related applications.

This project will develop novel compute-in-memory architectures including associative memory-based architectures to utilize approximate computing, with the aim of reducing the inference latency and increasing the throughput in Edge-AI applications.

DC1.3-TUD "Analog in-memory brain-inspired edge processors for Edge AI"

(TBA)

Recruiting institution: Delft University of Technology, Delft, The Netherlands
Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla
Cross-sectoral co-supervisor: Dr. Saad Saleh, IMEC-NL, The Netherlands
Recruitment period: TBA
PhD studies: Delft University of Technology

DC background

(TBA)

Individual research project 

(TBA)

DC1.1-TUT “Detection and recovery reliability mechanisms for digital edge AI devices”

Michael Elias

Recruiting institution: Infineon Technologies, Germany
Supervisors: Prof. Wolfgang Ecker, Dr. Endri Kaja, Georg Georgakos
Cross-sectoral co-supervisor: Prof. Maksim Jenihhin, Tallinn University of Technology, Estonia
Recruitment period: 01.08.2025 – 31.07.2028 (36 months)
PhD studies: Tallinn University of Technology

DC background

Michael Elias was accepted into the Lebanese University's 5-year Master's program in Electrical and Electronics Engineering. During his third year, he was selected for a double degree program with Politecnico di Torino in Italy, where he pursued a Master's degree in Computer Engineering with a focus on Embedded Systems, ultimately earning dual Master's degrees from both universities.

During his time at Politecnico di Torino, he participated in various labs and projects that refined his skills in digital design, including the implementation of a RISC-V core and work with machine learning accelerators, utilizing industry-standard EDA tools like Synopsys Design Compiler and Siemens ModelSim. He developed a Python framework to facilitate study the impact of quantization and approximate computing against adversarial attacks in Convolutional Neural Networks.

Given his interdisciplinary background in digital design and machine learning, he is well-suited to undertake the proposed PhD project.

Individual research project 

The goal of this project is developing a hardened SoC against bit-flip faults caused by radiation. A use case for such SoC would be in automotive where safety is of great significance. The hardening techniques can be classified into two categories:

• Physical Radiation-Hardening Techniques: involves using insulating substrates, bipolar integrated circuits, radiation-tolerant SRAM, etc.

• Logical Radiation-Hardening Techniques: involves error correcting code memory, redundant elements (hardware, information, time, and software redundancy or lockstep architecture), watchdog timers, etc.

As part of this research, logical radiation-hardening techniques will be the main subject of investigation. After completing the literature review, additional hardening techniques might be considered. This will allow us to explore different combination of techniques to find Pareto-optimal combinations between power, performance, area and reliability.

DC1.5-IFAG “Detection and recovery mechanisms for analog edge AI hardware”

Zishu Chai

Recruiting institution: Infineon Technologies AG, Germany
Supervisors: Dr Endri Kaja
Cross-sectoral co-supervisor: Dr. Prof. Jaan Raik, Prof. Maksim Jenihhin, Tallinn University of technology, Estonia
Recruitment period: 29.08.2025 – 28.08.2028 (36 months)
PhD studies: Tallinn University of Technology, Estonia

DC background

Zishu Chai earned a Bachelor’s degree in Electrical engineering and Intelligent control from Shanghai Maritime university, China. She later completed a Master degree in Electrical Engineering at Delft University of Technology with specific track of Microelectronics. During the master education, she received the ASML Technology Scholarship as one of forty students selected worldwide that accomplish their studies in the Netherlands. To deepen the professional skills in mix-signal IC design, Zishu completed the one-year master graduation internship in NXP Semiconductors, the Netherlands, while focusing on the innovative front-end design of CAN transceiver in automotive ECUs, contributing to a remarkable improvement in EMC robustness and an overall design cost reduction. These experiences underpin her PhD research on analog design in the robustness improvement of edge AI hardware.

Individual research project 

This individual research project focuses on developing efficient and effective analog mechanisms in asynchronous chip communication and clock systems, with reliability and robustness as primary objectives. In-field mechanisms which are able to detect relevant deviations due to in-field faults (soft errors, ageing, etc.) are worked out. Furthermore, analog specific mechanisms to compensate for these deviations during run-time are investigated. Communication mechanisms to report the health status to higher hierarchical levels and to enable system reactions to serious hardware issues will complement these investigations. Mechanisms to stress the analog hardware or to emulate relevant stress will be implemented to enable verification of the developed assessment methods. Expected outcomes include proven methodology on how to implement mechanisms for measuring the health of analog blocks or sub-systems on a chip and re-usable blocks that simplify measurement, assessment, activation of recovery schemes, and even transfer of the information to a higher hierarchical level (e.g., supervision unit).

DC2.1-DUS “Virtual Prototyping as Hardware–Software Co-Design Methodology for Next-Generation Automotive Edge-AI”

Germano Berto Girondi

Recruiting institution: Dumarey Softronix Torino, Italy
Supervisors: Alberto Pisoni and Dr Alessandra Neri
Cross-sectoral co-supervisors: Prof Luca Sterpone and Dr Sarah Azimi, Politecnico di Torino, Italy
Recruitment period: 20.10.2025 – 31.08.2028 (34 months)
PhD studies: Politecnico di Torino, Italy

DC background

Germano Berto Girondi holds a bachelor’s degree in computer engineering from the Federal University of Rio Grande do Sul, where he worked as an undergraduate research assistant and contributed to paper publications at conferences such as VLSI-SoC and ICECS on topics related to electronic design automation and reliability. He also holds a master’s degree in microelectronics and real-time embedded systems from Université Grenoble Alpes, where he participated in an apprenticeship program with STMicroelectronics, working as a microelectronic engineer apprentice.

Individual research project 

The growing integration of Edge-AI workloads into automotive ECUs calls for platforms that support early architectural exploration, efficient execution, and seamless hardware–software co-design. This PhD project introduces a unified methodology that combines virtual prototyping, RISC-V architectural investigation, and rapid prototyping through FPGA to support the design of future automotive compute units.

Grounded in the industrial context of Dumarey Softronix and aligned with the scientific goals of the TIRAMISU consortium, the project focuses on enabling early design decisions and providing a flexible environment for validating Edge-AI execution strategies in heterogeneous embedded systems.

The research is structured around four complementary pillars:

1. Hybrid Virtual Platform: development of a SystemC–ISS co-simulation environment capable of modeling CPUs, MCUs, RISC-V soft-cores, AI accelerators (in high-level form), and automotive communication interfaces. This platform enables evaluation of timing, performance, and energy trade-offs well before hardware availability.

2. RISC-V Architectural Exploration: use of RISC-V as an open, customizable compute backbone to explore microarchitectural variants, lightweight ISA extensions for Edge-AI kernels, memory subsystems, and integration patterns for future automotive ECUs.

3. FPGA-Based Rapid Prototyping: adoption of FPGA platforms not as the final implementation of accelerators, but as a flexible tool for validating architectural hypotheses, testing configurations, accelerating design-space exploration, and enabling hardware–software co-verification in a controllable environment.

4. AI Deployment on Heterogeneous Automotive Architectures: creation of co-design flows to map AI workloads onto CPUs and domain-specific accelerators under constraints related to latency, energy efficiency, integration in automotive platforms, and real-time predictability.

The resulting methodology supports early-stage evaluation, guided design choices, and efficient exploration of heterogeneous architectures accelerating the development of the next generation of automotive Edge-AI ECUs.

DC2.2-TUT “Reliability estimation techniches for AI accelerators”

Gustavo Vilar de Farias

Recruiting institution: Dept. of Control and Computer Engineering,

Politecnico di Torino, Italy
Supervisors: Prof. Matteo Sonza Reorda, Prof. Esteban Rodriguez
Cross-sectoral co-supervisor: Dr. Alessandra Neri,Dumarey Softronix, Italy
Recruitment period: 18.03.2025 – 17.03.2028 (36 months)
PhD studies: Politecnico di Torino, Italy

DC background

Graduated in electrical engineering with an emphasis in electronics from the Federal University of Campina Grande (Brazil) and a master's degree in embedded systems and connected objects from Phelma - Grenoble INP (France). He was an intern at Synopsys and ARM and worked as a digital hardware designer at HwIt developing an ASIC to be used in the Brazilian particle accelerator (Sirius). His research interests cover microelectronics and computer architecture.

Individual research project 

In several domains it is crucial to estimate the real impact of faults in AI applications based on Neural Networks. Unfortunately, traditional methods are unfeasible due to the huge computational cost. The research activities will focus on the development of efficient solutions to estimate the reliability of AI accelerators, considering the different kinds of (temporary and permanent) faults that can affect the hardware. Cross-layer approaches will be explored taking into account both the hardware characteristics and architecture and the different software layers composing the system. The goal is to devise solutions for trading-off estimation accuracy and computational power requirements. The gathered results will enable the development of effective solutions for detecting permanent faults and hardening AI accelerators with permanent and transient faults.

DC2.3-CDNS “Analysis and improvement of fault tolerance and safety of AI accelerators”

Sergiu-Mohamed Abed

Recruiting institution: Cadence Design Systems, Germany
Supervisors: Dr. Ahmet Cagri Bagbaba, Connie O’Shea
Cross-sectoral co-supervisor: Prof. Matteo Sonza Reorda, Politecnico di Torino, Italy
Recruitment period: 13.01.2025 – 12.01.2028 (36 months)
PhD studies: Politecnico di Torino, Italy

DC background

Sergiu-Mohamed Abed obtained his BSc and MSc degrees in Computer Engineering from Politecnico di Torino (Turin, Italy) in 2021 and 2024, respectively. During his master's degree studies, he specialized in artificial intelligence and data analytics, having worked with various deep learning models such as Convolutional Neural Networks (CNNs), Long-Short Term Memory (LSTM), Generative Adversarial Networks (GANs) and Transformer-based models. For his thesis, he worked on reliability assessment and software-based hardening of hyperspectral image classifiers, during which he simulated transient faults on GPUs by injecting faults at the instruction set level to identify the most sensitive parts of the classifier and to modify them to mitigate the effects of the faults.

Individual research project 

The PhD project focuses on improving the fault tolerance and safety of AI accelerators using innovative Electronic Design Automation (EDA) methods. The selected AI accelerators will be analysed to assess their inherent fault tolerance and to identify safety critical components. The aim is to explore how hardware accelerators can be designed to incorporate high fault detection and correction mechanisms, and to identify areas where enhanced fault detection is required. Innovative methods to leverage EDA tool flows to efficiently detect and correct faults in AI accelerators will be developed, and traditional flows based on existing Cadence tools will be adapted to integrate AI capabilities.

DC2.4-CDNS "Development of high-level fault models for validation of AI accelerators"

(TBA)

Recruiting institution: Cadence Design Systems, Germany
Supervisors: Dr. Hans-Martin Bluethgen, Dr. Felipe Augusto da Silva
Cross-sectoral co-supervisor: Prof. Said Hamdioui, Delft University of Technology, Netherlands
Recruitment period: TBA
PhD studies: Delft University of Technology

DC background

(TBA)

Individual research project 

(TBA)

DC3.1-UCY "Efficient and robust hardware neural network model accelerators for Edge AI"

(TBA)

Recruiting institution: Fraunhofer-Gesellschaft, Germany
Supervisors: Dr. Benjamin Prautsch, Andy Heinig
Cross-sectoral co-supervisor: Dr. Felipe Augusto da Silva, Cadence Design Systems, Germany
Recruitment period: TBA
PhD studies: Delft University of Technology

DC background

(TBA)

Individual research project 

(TBA)

DC3.1-UCY "Efficient and robust hardware neural network model accelerators for Edge AI"

Dimitrios Stylianos Lampridis

Recruiting institution: KIOS Research and Innovation Center of Excellence,

Department of Electrical and Computer Engineering, University of Cyprus, Cyprus
Supervisors: Prof. Maria K. Michael and Prof. Theocharis Theocharides
Cross-sectoral co-supervisor: Dr. Saad Saleh, IMEC-NL, Netherlands
Recruitment period: 01.09.2025 – 31.08.2028 (36 months)
PhD studies: University of Cyprus, Cyprus

DC background

Dimitrios Stylianos Lampridis is a graduate of the Department of Computer Science and Engineering at the University of Ioannina in Greece (2025), holding a 5-year integrated master’s degree, with a strong inclination toward hardware design and a solid background in the testing and reliability of integrated circuits. During his studies, he served as a teaching assistant for the laboratory course on VLSI circuit design and developed proficiency in EDA tools (e.g., Cadence Virtuoso and Spectre) for both design and simulation of VLSI circuits. His research interests focus on the modeling and testing of manufacturing defects in memory structures employed in Neural Networks. Furthermore, in his diploma thesis, entitled “Testing of Resistive Defects in SRAM-based In-Memory Computing”, he gained research experience in defect modeling, design-for-testability, and testing methodologies for SRAM-based In-Memory Computing topologies. These experiences underpin his PhD research on understanding the behavior of neural networks at the hardware level, evaluating the reliability (in terms of hardware faults), and use hardware and technology metrics to develop a holistic approach (potentially through neural architecture search) that combines efficiency and robustness for hardware neural network model accelerators for Edge AI.

Individual research project 

This research project focuses on the robustification of (dynamic) neural networks for Edge AI systems, with particular emphasis on improving their reliability in the presence of hardware faults and their adaptability under varying operating conditions. The project is expected to achieve several major accomplishments. Advancing the understanding of neural network behavior at the hardware level, particularly when mapped onto emerging Processing-in-Memory (PiM) architectures, developing robust techniques for evaluating and mitigating hardware-induced vulnerabilities, and contributing to the broader TIRAMISU network by providing methodologies that can be adopted in the design of future reliable and efficient Edge AI hardware platforms, are some of the key goals and anticipated contributions of the project. By combining device-level reliability analysis with neural architecture search, this research aims to bridge the gap between hardware vulnerabilities and system-level robustness. The expected outcome is a set of reliable and efficient Edge AI solutions that can be deployed in real-world, resource-constrained environments.

DC3.2-UCY "Robustification of dynamic neural networks via contextual awareness and attention for edge AI"

Yobsan Bayisa Leta

Recruiting institution: KIOS Research and Innovation Center of Excellence,

Department of Electrical and Computer Engineering, University of Cyprus, Cyprus
Supervisors: Prof. Theocharis Theocharides, Prof. Maria K. Michael, Dr. Christos Kyrkou
Cross-sectoral co-supervisor: Dr. Felipe Augusto da Silva, Cadence Design Systems, Germany
Recruitment period: 15.05.2025 – 14.05.2028 (36 months)
PhD studies: University of Cyprus, Cyprus

DC background

Yobsan Bayisa Leta was selected for Ethiopian Betre-Science program by the Ethiopian Ministry of Science and Technology and received a scholarship from the Ethiopian government to pursue his bachelor’s degree in software engineering, which he completed in 2021 at the University of Electronic Science and Technology of China. He then earned his master’s degree in 2023 at the same university, funded by the Chinese Government Scholarship. His undergraduate thesis focused on Inference and Prediction in Big Data using Sparse Gaussian Process Methods, while his master’s thesis explored Multitask Visio-Linguistic Representation Learning using Pretrained Convolutional Feature Extractors and Transformer Models. In addition to publishing several research papers in collaboration with other scholars, Yobsan has contributed to multiple funded projects in China. Notably, he developed a deep learning model to visualize and predict vehicle-to-road collaboration using camera and LiDAR data for the “5G-V2X” grant project. He also designed and develop two lightweight models: one for predicting future data consumption across service centers and another for classifying fault detection alarm reports for maintenance, both of which were integrated into the provincial China Mobile Telecom portal system. Following this, Yobsan joined the Southern University of Science and Technology in Shenzhen, China, where he worked for one and a half years on Hardware-aware Evolutionary Multiobjective Neural Architecture Search with applications in image segmentation for factory automation and autonomous driving. This research experience and hand-on project aligns with his PhD research on Robustification of dynamic neural networks via contextual awareness and attention edge AI.

Individual research project 

This research focuses on the optimization of Deep Neural Networks (DNNs) for Edge AI, specifically on semantic segmentation for autonomous edge AI systems. The findings are expected to be generalized to other automation domains that rely on similar tasks. The primary objective is to address the inherently high accuracy and robustness demanded by safety-critical applications and the conflicting constraints of edge devices, including limited memory, low power consumption, and real-time processing requirements. The central focus of this work is to develop robust edge AI models, taking into consideration the resource-constrained conditions in which these models operate. My research will address challenges in applications such as semantic segmentation and other similar tasks, under adverse conditions induced by system faults at various levels, natural adversaries such as rain, fog, snow, and poor illumination, and adversarial attacks. In these cases, the generalization capabilities of conventional models often degrade performance and reliability significantly. To address this challenge, this research will develop a multifaceted optimization framework. At the architectural level, the research will explore hybrid models that adopt convolutional, transformer-like, and other structures to achieve an effective balance between local feature extraction and global contextual reasoning. Both manually designed architectures and Multi-Objective Neural Architecture Search (NAS) will be explored to automatically discover architectures that achieve an optimal balance between model size, energy consumption, and latency while maintaining high accuracy. At the learning paradigm level, the research will investigate continual learning, condition-incremental learning, domain-adaptive training methods, and other trends that yield state-of-the-art edge AI models. This multidisciplinary approach is expected to enable the models to maintain robust performance when faced with the non-stationary data distributions and adverse conditions typical of real-world environments. It will also use several model compression techniques, such as quantization, pruning, and knowledge distillation, to ensure the developed models can be deployed on resource-constrained devices. The expected outputs of this research include: the development of novel architectures optimized for robust segmentation in adverse conditions; the design of a NAS framework, including problem formulation and a new search space, to discover efficient and accurate models for Edge AI constraints; the formulation of a continual learning pipeline integrated within a holistic NAS framework to sustain model performance under dynamic conditions; and the establishment of a benchmark and systematic methodology for adapting advanced deep learning models to Edge AI, contributing to the development of resilient, scalable, and safety-critical applications.

DC3.3-PDT "Software-based hardening solutions for AI-based architectures"

Aobo Cui

Recruiting institution: Dept. of Control and Computer Engineering,

Politecnico di Torino, Italy
Supervisors: Prof. Luca Sterpone, Dr. Sarah Azimi
Cross-sectoral co-supervisor: Dr. Ahmet Cagri Bagbaba, Cadence Design Systems, Germany
Recruitment period: 07.02.2025 – 06.02.2028 (36 months)
PhD studies: Politecnico di Torino, Italy

DC background

Aobo Cui born in 1999 in Songyuan, Jilin Province, China. He earned his bachelor degree in Electronic Science and Technology from Beijing Jiaotong University(BJTU), Beijing, China in 2021. He then received his master degree in the same major from Beihang University(BUAA), Beijing, China in 2024, with the focus on hardware security and testability. The work of his master study can be learned through<A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC> in the proceeding of 2022 IEEE International Test Conference in Asia (ITC-Asia). He is currently a PhD student at Politecnico di Torino, in the Aerospace, Safety, and Computing (ASaC) Lab.

Individual research project 

As AI-driven tasks become increasingly complex, the demand for high-performance hardware accelerators such as GPUs and TPUs has grown substantially. This research aims to develop efficient, reliable, and cost-effective hardware-hardened solutions tailored for artificial intelligence applications. The study will adopt a hierarchical approach, addressing optimization strategies from the circuit cell layout level up to the entire system architecture. The anticipated outcomes include modern process solutions that enhance resilience and efficiency in high-radiation environments, such as space, through both circuit structure-based and layout-based optimization techniques.

DC3.4-TUT "Neural Architecture Search framework for efficient and reliable hybrid CNN-Transformer models for Edge AI""

Hafsa Tanveer

Recruiting institution: Dept. of Computer Systems, Tallinn University of Technology, Estonia
Supervisors: Prof. Masoud Daneshtalab, Prof. Maksim Jenihhin
Cross-sectoral co-supervisor: Dr. Wolfgang Ecker; Infineon Technologies, Germany
Recruitment period: 02.09.2025 – 31.08.2028 (36 months)
PhD studies: Tallinn University of Technology

DC background

Hafsa Tanveer began her academic journey at the National University of Sciences and Technology (NUST), Pakistan’s leading engineering institution, where she completed her Bachelor’s in Computer Engineering. Awarded a prestigious full scholarship, she pursued her M.Sc. in Computer Science at the University of Cincinnati, USA, serving as a Teaching Assistant and conducting thesis research on advanced deep learning methods for time-series data analysis and forecasting. Returning to Pakistan, she contributed as a Research Associate at the Digital Pakistan Lab, spearheading the machine learning components of large-scale healthcare initiatives. She later transitioned into academia as a Lecturer in Computer Engineering department at Air University, combining teaching with applied research, while also working as a Machine Learning Engineer for Power Technology Research, a US-based firm. These experiences across academia, industry, and research have shaped her PhD pursuit of designing a Neural Architecture Search framework for efficient and reliable hybrid CNN–Transformer models tailored for Edge AI.

Individual research project 

This PhD project focuses on developing a neural architecture search (NAS) framework for hybrid CNN–Transformer models tailored for Edge AI. The central objective is to design a supernetwork that is efficient, robust, and reliable, while being capable of generating specialised subnetworks for diverse hardware platforms without extensive retraining. The research introduces three complementary directions: (a) Investigating and proposing novel training algorithms to enhance robustness, reliability, and accuracy of subnetworks within the supernetwork; (b) Developing fast and resource-efficient search algorithms for extracting optimal subnetworks from the trained supernetwork; and (c) Designing surrogate predictor models to evaluate critical performance metrics—including accuracy, robustness, reliability, and latency—across full-precision and quantized implementations.

Expected outcomes include a versatile NAS framework capable of producing hardware-adaptable subnetworks, benchmarks demonstrating accuracy–efficiency trade-offs for edge devices, and open-source artefacts (code, datasets, and trained models) released for the broader research community. This work will advance the state of the art in Edge AI by bridging architectural innovation with hardware-aware reliability, contributing toward AI systems that are not only high-performing but also dependable in long-term deployment.

DC3.5-TUD "Reliability-aware mapping and optimization techniques for Edge AI"

(TBA)

Recruiting institution: Delft University of Technology, Delft, The Netherlands
Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla
Cross-sectoral co-supervisor: Dr. Manolis Sifalakis, IMEC-NL, The Netherlands
Recruitment period: TBA
PhD studies: Delft University of Technology

DC background

(TBA)

Individual research project 

(TBA)

DC4.1-BFH "Human Oversight and Innovation Management for Edge AI R&D&I Ecosystems"

Benedek Fülöp

Recruiting institution: Berner Fachhochschule, Switzerland
Supervisors: Dr. Christian Hopp, Prof. Dr. Branka Hadji Misheva
Cross-sectoral co-supervisor: TUT, IMEC, UCY
Recruitment period: 01.09.2025 – 31.08.2028 (36 months)
PhD studies: Berner Fachhochschule, Switzerland

DC background

Benedek Fulop completed their Bachelor’s degree in Economics at the University of Warwick, studying one year in Global Sustainable Development and Economics. Following, they worked as a Data Finance analyst for Amazon Europe Middle-Mile then Global transportation, developing methodology and analytics platforms and tools with international teams. Later they gained their MS.c at the University of Amsterdam in Data Science and Business Analytics. During their studies they focused on developing more contextual explainability algorithms resulting in the CoalitionExplainer implementation in the SHAP library. These experiences underpin their PhD research on Human-Oversight of Edge-AI systems.

Individual research project 

This research project focuses on developing frameworks, tools, and requirements for Edge AI systems that ensure fundamental rights, ethical practices, and responsible AI design principles. Given the visibility of Edge-AI deployments is restricted while their effects on their social and physical environments are more immediate. This research will address the deeply entangled nature of AI, and especially edge-AI, by using and developing participatory research methods to ensure stakeholder visibility and involvement and build community of situationally aware researchers.

Expected outcomes include: 1. A methodology and praxis for human-centric Edge-AI development. 2. Inclusive focus-group on the situational awareness, needs, and perspectives of Edge-AI stakeholders. 3. An ecosystem of technical tools and methods for visibility, understanding, and intervention throughout the lifecycle of systems. 4. Classification of TIRAMISU AI systems along the risk categories of the EU AI Act; Risk assessment to ensure the EU AI Risk Mitigation activities are met, specifically on data governance, technical documentation and traceability, transparency, human oversight, accuracy and robustness of AI system characteristics and interactions.

DC4.2-BFH"Case Study of Innovation Management for Edge AI Hardware Design Flow"

Xiangrui Zeng

Recruiting institution: Institute of Applied Data Science & Finance (IADSF), Bern University of Applied Sciences, Switzerland
Supervisors: Prof. Christian Hopp, Prof. Branka Hadji Misheva & Dr. Gernot Pruschak
Cross-sectoral co-supervisor: Prof. Alessandra Colombelli & Dr. Alessandra Neri
Recruitment period: 01.06.2025 – 31.05.2028 (36 months)
PhD studies: Bern University of Applied Sciences, Switzerland

DC background

Xiangrui Zeng got his master’s degree in business administration at Xi’an Jiaotong University in the PR China. His main research interests are in Innovation and Entrepreneurship. During his studies, he built a solid academic foundation as supported by his got excellent grade and by winning the following prizes: national scholarship, special academic scholarship, excellent graduate cadres, outstanding university graduates of the Sichuan province, and winner of the Challenge Cup for college students in the Sichuan province. Moreover, the case study “Building a Sharing Platform for Fast Repair of Catering Equipment in Catering Enterprises: The Entrepreneurial Path of Zao Wang Bang” conducted during his Master studies was honored as one of the 100 Best Cases by China Management Case Center in 2022. He also had already published a research paper entitled “Employee stock ownership plans and corporate environmental, social, and governance performance: Evidence from China” in the Review of Managerial Science during his Master studies. After graduation, he worked as an industry research fellow for nearly 3 years in Hunan Caixin Trust Co., Ltd. and also launched an entrepreneurial program as a co-founder aimed at using large language models to solve pain points in board game instructions. These experiences provided the perfect baseline for starting the PhD in innovation management for edge AI hardware design flow.

Individual research project 

The dissertation focuses on the commercialization opportunities arising from innovative edge AI software and hardware solutions. This implies studying and actively engaging in the research and innovation management from early-stage research up to the phase of technology transfer (patenting, spin-offs, etc.) while addressing technical, regulatory, and environmental challenges. Thus, the dissertation addresses an important paradoxical challenge for nowadays researchers and innovators (Owen-Smith & Powell, 2001). After all, existing knowledge of the management R&D&I initiatives is inconclusive in understanding the antecedents of innovation success in interdisciplinary deep-tech research projects like the Edge AI domain due to its limited generalizability (Beck et al., 2022). Especially researchers in Europe who engage in basic research frequently lack an entrepreneurial mindset fostering commercialisation activities (Feenstra et al., 2024). The dissertation therefore theoretically develops and empirically validates an interaction model explaining the antecedents of successful deep-tach commercialisation. The findings will provide valuable implications for innovation and valorisation actions to ensure the successful exploitation of research results by identifying the stakeholders’ groups and commercialisation pathways with the highest capacity for market applications.